APG Test Consultants, Inc.

APG HP3070 Split Fixturing Concepts

The growing complexities of today’s electronic circuit boards are pushing manufacturing and test to new limits. To successfully produce high node count boards of the best quality, it is imperative that the electronic manufactures identify new ways to measure and understand the manufacturing process. APG’s split fixture process is an example of the innovation required to deal with the ever-increasing complexity of tomorrow’s manufacturing problems. In this is example an 8300 node board that was previously tested on one fixture with limited test coverage has now been developed on two separate fixtures with full test access at a reduced price with significant reduction in test development time.

As manufacturing processes mature and improve high node count boards are becoming a viable solution for condensing and integrating multi-boards systems into smaller and more efficient packages. The test methods used to maintain manufacturing process improvement must change to accommodate this increased complexity. Increasing available test-head resources will not completely eliminate the problem. Testing an 8300 node board on one fixture lends itself to longer fixture lead times (3 times that of the standard 5 day turn) and time consuming test development and debug, ultimately resulting in loss of test coverage and increasing costs for a substandard board test product.

To successfully deliver a test application on two separate fixtures for a high node count board a robust manufacturing process is required. In this split fixture example the board was initially developed assuming an unlimited number of test-head resources are available. The cad data was translated using the standard APG translator "XC", an in-house translation solution. This is a highly configurable translator which quickly produces the required HP board output files as well as generating the appropriate mylar plots to be used with the bare board for physical nodal access evaluation. Additional steps were also taken to allow the use of APG’s boardless fixturing process on the extremely dense board consisting primarily of fine pitch double sided BGA and surface mount technology. Program generation was then completed on the entire board to produce a baseline for test resource requirements for the complete board’s circuitry. The next phase was a completely manual process for identifying circuit clusters that functioned together using the board schematics. This is the only manual step in the test development process.

After evaluating the board circuit description and completing the initial program generation the process was taken over by a set of utilities which split the application in half. Each fixture maintains access to a common set of all power nodes, all boundary scan chain nodes (13 chains consisting of 38 devices) and all digital test disabling nodes in addition to the nodes required to perform the tests on the devices specific to each test program. The entire board must be able to be disabled on each fixture utilizing the common set of nodes. To achieve access to the required nodes, the utilities gathered data for each "device.pin" and its respective node. The board_xy files were then automatically edited to change the attributes to no-access for each node that the utility deemed test resources were not required. Both nodal and device attribute sections of the board_xy files were changed to reflect that access was not available to nodes that were not being used to test the board on the associated fixture. Drilled alternate nodes that were not potential test resources in very dense 50mil areas were also automatically removed from the fixture reducing the initial 50mil probe count by 1150 probes. This step alone significantly lowered the cost of the test fixtures. The utilities also analyzed digital devices that required test-jet and updated the appropriate TJ entries in the board file. Analog null-tests were evaluated to ensure that each test that was not a null-test in the initial development remained testable in at least one of the final test programs. The original libraries and board information were then used to develop the two sets of board and fixture files. This process was relatively trivial due the original board files that had already undergone the initial program development and compilation. The result was two separate fixtures, one with approximately 3300 nodes, 3800 wires containing 74 test-jet and the other with 3100 nodes, 3600 wires containing 52 test-jet. Of the 8300 nodes, 2600 nodes on the board did not need test resources (single pin no-connects). Access was achieved on each of the remaining 5700 nodes between the two fixtures.

Each fixture has been manufactured using APG’s newly developed linear vacuum sealing lid design. This type of design reduces the weight of each fixture by an estimated 40-45 lb. and represent a 4 percent reduction in cost per fixture. This also provides the safest environment for testing boards that are being powered using -48V at between 4 and 5 amps while allowing for complete visual access to the board being tested. The top gate contains no metal bars that can become lose or obstruct the view of the board and accommodates 6300 lb. of evenly distributed downward atmospheric pressure to move the board on to a internally reinforced probe field with a completely linear motion. Each of the 700 to 800 50 mil probes per fixture are guided to achieve consistent successful registration with APG’s two piece guide blocks that are also machined to provide the bottom side BGA support which is critical to prevent damage to sensitive BGA solderability.

Maintaining and continuing to improve this automatic HP3070 Split Fixture process along with APG’s overall test application and fixturing processes are the key to providing cost effective innovative solutions for HP3070 board test. Combining programming and fixture fabrication expertise in one facility allows APG to experience process improvement and innovation daily.

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