APG Test Consultants, Inc.

Advanced Programming is our business…

Our Programming staff are specialists in many of the advanced HP 3070 features such as Interconnect Plus boundary scan, high performance analog/digital test techniques and serial telecommunications test. Our test programs are uniquely developed to maximize yield, minimize test time, and provide high fault coverage. We achieve our client's quality goals by applying state of the art test methodologies to all of our HP 3070 programs. APG provides the following design and test services:

· Installation of fixture and test program on customer site

· Fast test program turns and quotation services.

· Complete on-site customer training and support services.

· Custom ASIC, processor, MCM and mixed library development.

· Interconnect Plus and Silicon Nail boundary scan testing.

· VXI functional test programming, HP VEE device drivers, VEE Test Mains.

· APG provides complete IEEE-1149.1 design and simulation services in Verilog , VHDL & BSDL.

APG has provided test programs and design consulting services to the world's largest hi-tech and contract manufacturing corporations. APG was awarded Hewlett-Packard's prestigious "User Referenced Solution" status and is a member of the Hewlett-Packard Channel Partner program. APG was chosen by the HP 3070 Applications Center to develop "Bench Mark" test programs for the HP 3070. APG’s programs have been used by Hewlett-Packard in competitive sales environments where very high quality programs are essential. For more information on APG’s "Bench Mark" quality programming call us today at (303) 702-0007.

Automatic JTAG 1149.1 Simulation Environment

This software consists of three automatically generated Verilog modules.

HP 3070 PCF to Verilog Conversion

This module converts HP 3070 PCF vectors into a custom Verilog vector format for device simulations. These simulation vectors are used with APG’s "Verilog Test Bench" (VTB) to verify compliance with the IEEE-1149.1 boundary scan standard. APG can provide all the vectors necessary for the compliance simulation or the customer can generate them using an HP 3070 development station.

Automatic Verilog Simulation Environment (VTB)

This module uses the BSDL file and the devices top level Verilog module to generate a boundary scan simulation environment. This module attaches the device inputs, outputs and bi-directional ports automatically to the VTB stimulus driver and receiver module.

IEEE-1149.1 Simulation Diagnostics.

This module post processes the Verilog output file (verilog.log) created during the simulation and provides explicit diagnostics to enable the designer to debug the design. This module reports the simulation time of every failing event, provides the failing pin/port and boundary scan cell information and displays the expected TAP state and instruction information for each failure.

Boundary Scan Design & Test Consulting Services

APG offers state of the art consulting services for IEEE-1149.1 boundary scan designs. We specialize in providing complete boundary scan solutions to our customers. APG can develop BSDL (Boundary Scan Description Language) files, design TAP controllers, custom boundary scan cells and generate full IEEE-1149.1 compliance check simulations. APG removes the risk of non-compliance by providing a complete set of simulation vectors for your design. APG uses Hewlett-Packards " Verify BSDL" vectors to generate the industry’s most complete compliance simulation and test vector set. Verify BSDL has become the industries defacto standard for compliance checking IEEE-1149.1 components. APG can also provide post fabrication testing services for your silicon. APG can verify your hardware in an in-circuit test environment and develop interconnect tests between your device and other commercially available products. Industry leaders in boundary scan such as Panasonic, ATT and StorageTek all use closed loop design procedures to develop and verify IEEE-1149.1 compliant devices.

BSDL files

APG offers complete BSDL development service. Our consultants will work with IC designers to define boundary scan topology and develop:

Special / Private instructions.
Fault injection structures for system level diagnostic verification.
Special BIST requirements and structures.
Identification register code or special Instruction Capture codes.
Design unique boundary scan cells that are not defined in the STD_1149_1_1990.
Update STD_1149_1_1990 VHDL include files for test systems.
Develop BSDL files to the new STD_1149_1_1994 standard
Update STD_1149_1_1990 VHDL to STD_1149_1_1994 VHDL

APG’s Closed Loop Scan Process:

APG's Closed Loop Scan process provides a closed loop design path for boundary scan development. A full set of IEEE-1149.1 simulation vectors are provided for each design. Any errors in the scan design are detected by the simulation and "fed back" to the design model. After a successful simulation run the device is ready for fabrication. The final stage of testing involves applying verify BSDL test vectors to the silicon and testing the interconnect capability with other IEEE-1149.1 devices.

Boundary Scan Verification Services